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rt8020 ? ds8020-06 march 2012 www.richtek.com 1 ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. applications mobile phones personal information appliances wireless and dsl modems mp3 players portable instruments ordering information pin configurations (top view) wdfn-12l 3x3 dual high-efficiency pwm step-down dc/dc converter features 2.5v to 5.5v input range adjustable output from 0.6v to v in 1.2v, 1.3v, 1.8v, 2.5v and 3.3v fixed/ adjustable output voltage 1a output current 95% efficiency no schottky diode required 50ua quiescent current per channel 1.5mhz fixed frequency pwm operation small 12-lead wdfn package rohs compliant and 100% lead (pb)-free general description the rt8020 is a dual high-efficiency pulse-width- modulated (pwm) step-down dc/dc converter. it is capable of delivering 1a output current over a wide input voltage range from 2.5v to 5.5v, the rt8020 is ideally suited for portable electronic devices that are powered from 1-cell li-ion battery or from other power sources within the range such as cellular phones, pdas and other hand- held devices. two operational modes are available : pwm/low-dropout auto-switch and shutdown modes. internal synchronous rectifier with low r ds(on) dramatically reduces conduction loss at pwm mode. no external schottky diode is required in practical application. the rt8020 enters low-dropout mode when normal pwm cannot provide regulated output voltage by continuously turning on the upper pmos. the rt8020 enter shutdown mode and consumes less than 0.1 a when en pin is pulled low. the switching ripple is easily smoothed-out by small package filtering elements due to a fixed operation frequency of 1.5mhz. this along with small wdfn-12l 3x3 package provides small pcb area application. other features include soft start, lower internal reference voltage with 2% accuracy, over temperature protection, and over current protection. vin2 lx2 nc1 fb1 en2 nc2 fb2 lx1 gnd gnd en1 vin1 11 10 9 1 2 3 4 5 12 67 8 gnd 13 rt8020 package type qw : wdfn-12l 3x3 (w-type) lead plating system p : pb free g : green (halogen free and pb free) output voltage : vout1/vout2 default : adjustable a : 3.3v/1.8v b : 3.3v/1.3v c : 3.3v/1.2v d : 2.5v/1.8v note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes.
rt8020 2 ds8020-06 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit figure 1. adjustable voltage regulator ( ) + = en2 nc2 fb2 vin2 lx2 fb1 rt8020 1 2 4 9 10 11 gnd lx1 gnd 8 5 nc1 3, exposed pad (13) 12 v out2 l2 2.2h 850k 4.7f c in2 22pf vin1 7 6 en1 v in1 4.7f l1 2.2h r22 4.7f v out1 850k 22pf 4.7f r12 v in2 c11 c out1 c in1 c out2 c21 r11 r21 marking information rt8020apqw c2-ym dnn rt8020agqw c2- : product code ymdnn : date code rt8020bpqw c3= : product code ymdnn : date code c3=ym dnn rt8020bgqw c3-ym dnn c3- : product code ymdnn : date code c4=ym dnn c4-ym dnn c5=ym dnn c5-ym dnn rt8020cpqw c2=ym dnn c2= : product code ymdnn : date code c4- : product code ymdnn : date code rt8020cgqw c4= : product code ymdnn : date code rt8020dpqw c5- : product code ymdnn : date code rt8020dgqw c5=: product code ymdnn : date code
rt8020 3 ds8020-06 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 2. fixed voltage regulator v outx = 1.2v, 1.3v, 1.8v, 2.5v or 3.3v functional pin description pin no. pin name pin function 1 vin2 power input of channel 2. 2 lx2 pin for switching of channel 2. 3, 9, exposed pad (13) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 4 fb1 feedback of channel 1. 5, 11 nc1, nc2 no connection or connect to v in . 6 en1 chip enable of channel 1 (active high). v en1 Q v in1. 7 vin1 power input of channel 1. 8 lx1 pin for switching of channel 1. 10 fb2 feedback of channel 2. 12 en2 chip enable of channel 2 (active high). v en2 Q v in2. en2 nc2 fb2 vin2 lx2 fb1 rt8020 1 2 4 9 10 11 gnd lx1 gnd 8 5 nc1 12 v out2 l2 2.2h c in2 4.7f vin1 7 6 en1 v in1 4.7f l1 2.2h 4.7f v out1 4.7f v in2 c out1 c in1 c out2 3, exposed pad (13)
rt8020 4 ds8020-06 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram driver control logic current limit detector osc and shutdown control current sense v ref fbx gnd lxx pwm comparator slope compensation error amplifier uvlo and power good detector rc comp enx vinx rs1 rs2
rt8020 5 ds8020-06 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. absolute maximum ratings (note 1) supply input voltage, v in1 , v in2 ---------------------------------------------------------------------------------- ? 0.3v to 6.5v en1, fb1, lx1, en2, fb2 a nd lx2 pin voltage -------------------------------------------------------------- ? 0.3v to (v in + 0.3v) power dissipation, p d @ t a = 25 c wdfn-12l 3x3 -------------------------------------------------------------------------------------------------------- 1.667w package thermal resistance (note 2) wdfn-12l 3x3, ja -------------------------------------------------------------------------------------------------- 60 c/w wdfn-12l 3x3, jc -------------------------------------------------------------------------------------------------- 8.2 c/w lead temperature (soldering, 10 sec.) -------------------------------------------------------------------------- 260 c junction temperature ------------------------------------------------------------------------------------------------ 150 c storage temperature range --------------------------------------------------------------------------------------- ? 65 c to 150 c esd susceptibility (note 3) hbm (human body mode) ----------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------------------- 200v electrical characteristics parameter symbol test conditions min typ max unit channel 1 and channel 2 input voltage range v in 2.5 -- 5.5 v under voltage lock out threshold uvlo -- 1.8 -- v hysteresis -- 0.1 -- v quiescent current i q i ou t = 0ma, v fb = v ref + 5% -- 50 70 a shutdown current i shdn en = gnd -- 0.1 1 a reference voltage v ref for adjustable output voltage 0.588 0.6 0.612 v adjustable output voltage range v out (note 6) v ref -- v in ? v v v out v in = 2.5v to 5.5v, v out = 1.2v 0a < i out < 1a ? 3 -- 3 % v out v in = 2.5v to 5.5v, v out = 1.3v 0a < i out < 1a ? 3 -- 3 % v out v in = 2.5 to 5.5v, v out = 1.8v 0a < i out < 1a ? 3 -- 3 % v out v in = v out + v to 5.5v (note 5) v out = 2.5v, 0a < i ou t < 1a ? 3 -- 3 % output voltage accuracy fix v out v in = v out + v to 5.5v (note 5) v out = 3.3v, 0a < i ou t < 1a ? 3 -- 3 % recommended operating conditions (note 4) supply input voltage ------------------------------------------------------------------------------------------------- 2.5v to 5. 5v junction temperature range --------------------------------------------------------------------------------------- ? 40 c to 125 c ambient temperature range --------------------------------------------------------------------------------------- ? 40 c to 85 c (v in = 3.6v, v out = 2.5v, v ref = 0.6v, l = 2.2uh, c in = 4.7 f, c out = 10 f, t a = 25 c, i max = 1a unless otherwise specified)
rt8020 6 ds8020-06 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit output voltage accuracy adjustable v out v in = v out + v to 5.5v (note 5) 0a < i out < 1a ? 3 -- 3 % fb input current i fb v fb = v in ? 50 -- 50 na v in = 2.5v -- 0.38 -- r ds(on) of p-mosfet r ds(on)_p i out = 200ma v in = 3.6v -- 0.28 -- v in = 2.5v -- 0.35 -- r ds(on) of n-mosfet r ds(on)_n i out = 200ma v in = 3.6v -- 0.25 -- p-channel current limit i lim_p v in = 2.5v to 5.5 v 1.4 1.5 -- a logic-high v en_h v in = 2.5v to 5.5v 1.5 -- v in en input voltage logic-low v en_l v in = 2.5v to 5.5v -- -- 0.4 v oscillator frequency f osc v in = 3.6v, i out = 100ma 1.2 1.5 1.8 mhz thermal shutdown temperature t sd -- 160 -- c maximum duty cycle 100 -- -- % lx leakage current i lx v in = 3.6v, v lx = 0v or v lx = 3.6v ? 1 -- 1 a note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. v = i out x p rds(on) note 6. guarantee by design.
rt8020 7 ds8020-06 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 output current (a) efficiency (%) v in = 3.6v v in = 4.2v v in = 5.0v v out = 3.3v, l = 4.7 h, c out = 4.7 f efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 output current (a) efficiency (%) v in = 5.0v v in = 3.6v v in = 3.3v v in = 2.5v v out = 1.2v, l = 4.7 h, c out = 4.7 f efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 output current (a) efficiency (%) v in = 5.0v v in = 3.6v v in = 3.3v v in = 2.5v v out = 1.2v, l = 2.2 h, c out = 10 f en pin threshold vs. temperature 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature en pin threshold (v) v in = 3.6v, v out = 1.2v, i out = 0a rising falling ( c) uvlo threshold vs. temperature 1.20 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature uvlo threshold (v) ( c) v out = 1.2v, i out = 0a rising falling en pin threshold vs. input voltage 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 input voltage (v) en pin threshold (v) v out = 1.2v, i out = 0a rising falling en pin threshold vs. input voltage
rt8020 8 ds8020-06 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. output current limit vs. temperature 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature output current limit (a) ( c) v out = 1.2v v in = 5.0v v in = 3.6v v in = 3.3v switching frequency vs. temperature 1.2 1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature frequency(khz) v in = 3.6v, v out = 1.2v, i out = 300ma ( c) output voltage vs. loading current 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 1.225 1.230 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 loading current (a) output voltage (v) v in = 5.0v v in = 3.6v output voltage vs. temperature 1.15 1.16 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1.24 1.25 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature output voltage (v) v in = 3.6v, i out = 0a ( c) switching frequency vs. input voltage 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 input voltage (v) frequency(khz) v in = 3.6v, v out = 1.2v, i out = 300ma output current limit vs. input voltage 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5 input voltage (v) output current limit (a) v out = 1.2v @ t a = 25 c
rt8020 9 ds8020-06 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. power on from v in v in (2v/div) time (250 s/div) v out (1v/div) i lx (1a/div) v in = 3.6v, v out = 1.2v, i out = 10ma load transient response time (50 s/div) v out (50mv/div) i out (500ma/div) v in = 3.6v, v out = 1.2v, i out = 50ma to 0.5a power on from en v en (2v/div) time (100 s/div) v out (1v/div) i in (500ma/div) v in = 3.6v, v out = 1.2v, i out = 10ma power on from en v en (2v/div) time (100 s/div) v out (1v/div) i in (500ma/div) v in = 3.6v, v out = 1.2v, i out = 1a load transient response time (50 s/div) v out (50mv/div) i out (500ma/div) v in = 3.6v, v out = 1.2v, i out = 50ma to 1a power off from en v en (2v/div) time (100 s/div) v out (1v/div) i lx (1a/div) v in = 3.6v, v out = 1.2v, i out = 10ma
rt8020 10 ds8020-06 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ripple time (500ns/div) v out (10mv/div) v lx (2v/div) v in = 3.6v, v out = 1.2v, i out = 1a ripple time (500ns/div) v out (10mv/div) v lx (2v/div) v in = 5.0v, v out = 1.2v, i out = 1a load transient response time (50 s/div) v out (50mv/div) i out (500ma/div) v in = 5.0v, v out = 1.2v, i out = 50ma to 1a load transient response time (50 s/div) v out (50mv/div) i out (500ma/div) v in = 5.0v, v out = 1.2v, i out = 50ma to 0.5a
rt8020 11 ds8020-06 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. applications information the basic rt8020 application circuit is shown in typical application circuit. external component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by c in and c out . inductor selection for a given input and output voltage, the inductor value and operating frequency determine the ripple current. the ripple current i l increases with higher v in and decreases with higher inductance. having a lower ripple current reduces the esr losses in the output capacitors and the output voltage ripple. highest efficiency operation is achieved at low frequency with small ripple current. this, however, requires a large inductor. a reasonable starting point for selecting the ripple current is i l = 0.4(i max ). the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or permalloy cores. actual core loss is independent of core size for a fixed inductor value but it is very dependent on the inductanc e selected. as the inductance increases, core losses decrease. however, increas ed inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates ? hard ? , which means that inductance collapses abruptly when the peak design current is exceeded. this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further de-rate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v out , is determined by : ? ? ? ? ? ? ? ? ? ? ? ? ? = in out out l v v 1 l f v i ? ? ? ? ? ? ? ? ? ? ? ? ? = in(max) out l(max) out v v 1 i f v l ? ? ? ? ? ? + out l out 8fc 1 esr i v 1 v v v v i i out in in out out(max) rms ? = this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate energy but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depend on the price vs. size requirements and any radiated field/emi requirements. c in and c out selection the input capacitance, c in , is needed to filter the trapezoidal current at the source of the top mosfet. to prevent large ripple voltage, a low esr input capacitor sized for the maximum rms current should be used. rms current is given by :
rt8020 12 ds8020-06 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. the output ripple is highest at maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long-term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. output voltage programming the resistive divider allo ws the fb pi n to sense a fraction of the output voltage as shown in figure 3. figure 3. setting the output voltage for adjustable voltage mode, the output voltage is set by an external resistive divider according to the following equation : v out = v ref x (1+ r1/r2) where v ref is the internal reference voltage (0.6v typical) efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. efficiency can be expressed as : efficiency = 100% ? (l1+ l2+ l3+...) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: v in quiescent current and i 2 r losses. the v in quiescent current loss dominates the efficiency loss at very low load currents whereas the i 2 r loss dominates the efficiency loss at medium to high load currents. in a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1.the v in quiescent current oppears due to two components : the dc bias current and the gate charge currents. the gate charge current results from switching the gate capacitance of the internal power mosfet switches. each time the gate is switched from high to low to high again, a packet of charge q moves from v in to ground. the resulting q/ t is the current out of v in that is typically larger than the dc bias current. in continuous mode, i gatechg = f(q t + q b ) where q t and q b are the gate charges of the internal top and bottom switches. both the dc bias and gate charge losses are proportional to vin and thus their effects will be more pronounced at higher supply voltages. 2. i 2 r losses are calculated from the resistances of the internal switches, r sw and external inductor r l . in continuous mode the average output current flowing rt8020 fb gnd v out r1 r2
rt8020 13 ds8020-06 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load (esr), where esr is the effective series resistance of c out . i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. layout considerations follow the pcb layout guidelines for optimal performance of rt8020. ` for the main current paths, keep their traces short and wide. ` put the input capacitor as close as possible to the device pins (vin and gnd). ` lx node is with high frequency voltage swing and should be kept small area. keep analog components away from lx node to prevent stray capacitive noise pick-up. ` connect feedback network behind the output capacitors. keep the loop area small. place the feedback components near the rt8020. ` connect all analog grounds to a command node and then connect the command node to the power ground behind the output capacitors. through inductor l is ? chopped ? between the main switch and the synchronous switch. thus, the series resistance looking into the lx pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (d c) is shown as follows : r sw = r ds(on)top x dc + r ds(on)bot x (1 ? dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus, to obtain i 2 r losses, simply add r sw to r l and multiply the result by the square of the average output current. other losses including c in and c out esr dissipative losses and inductor core losses generally account for less than 2% of the total loss. thermal considerations the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = ( t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of rt8020 dc/dc converter, where t j(max) is the maximum junction temperature of the die and t a is the ambient temperature. the junction to ambient thermal resistance ja is layout dependent. for wdfn-12l 3x3 packages, the thermal resistance ja is 60 c/w on the standard jedec 51-7 four-layers thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c) / (60 c/w) = 1.667w for wdfn-12l 3x3 packages the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . for rt8020 packages, the figure 4 of de- rating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. figure 4. de-rating curves for rt8020 package 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) four-layer pcb
rt8020 14 ds8020-06 march 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 1. recommended inductors component supplier series inductance ( h) dcr (m ) current rating (ma) dimensions (mm) taiyo yuden nr 3015 2.2 60 1480 3 x 3 x 1.5 taiyo yuden nr 3015 4.7 120 1020 3 x 3 x 1.5 sumida cdrh2d14 2.2 75 1500 4.5 x 3.2 x 1.55 sumida cdrh2d14 4.7 135 1000 4.5 x 3.2 x 1.55 gotrend gtsd32 2.2 58 1500 3.85 x 3.85 x 1.8 gotrend gtsd32 4.7 146 1100 3.85 x 3.85 x 1.8 table 2. recommended capacitors for c in and c out component supplier part no. capacitance ( f) case size tdk c1608jb0j475m 4.7 0603 tdk c2012jb0j106m 10 0805 murata grm188r60j475ke19 4.7 0603 murata grm219r60j106me19 10 0805 taiyo yuden jmk107bj475ra 4.7 0603 taiyo yuden JMK107BJ106MA 10 0603 taiyo yuden jmk212bj106rd 10 0805
rt8020 15 ds8020-06 march 2012 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 d 2.950 3.050 0.116 0.120 d2 2.300 2.650 0.091 0.104 e 2.950 3.050 0.116 0.120 e2 1.400 1.750 0.055 0.069 e 0.450 0.018 l 0.350 0.450 0.014 0.018 w-type 12l dfn 3x3 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options

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